Frequency-to-digital converter (FDC) based PLLs are widely used n wireless communication systems because they provide many of the advantage of both analog and digital PLLs. However, the circuit design of FDC based PLL faces a trade off between noise suppression and bandwidth extension. For example, when a high resolution ADC is employed to suppress the quantization noise component of the PLL's phase noise, the bandwidth of the PLL becomes narrow and hard to be used in intermediate frequency (IF) application.
Therefore, there is a need to provide a PLL capable of suppressing the quantization noise and extending the bandwidth.